Microcomponent Massive MIMO Arrays

ABSTRACT

A microcomponent massive MIMO array is presented. The microcomponent massive array includes a general purpose processor and an integrated power amplifier and transmitter device including a software defined radio (SDR) and a plurality of polar power amplifiers (PAs) disposed on a single integrated circuit, wherein the integrated power amplifier and transmitter device is in communication with the general purpose processor. The microcomponent massive MIMO array further includes an antenna array in communication with the integrated power amplifier and transmitter device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.16/286,548, filed Feb. 26, 2019 which claims priority under 35 U.S.C. §119(e) to U.S. Provisional Pat. App. No. 62/635,294, entitled“Microcomponent Massive MIMO Arrays” and filed Feb. 26, 2018, andfurther claims priority under 35 U.S.C. § 119(e) to U.S. ProvisionalPat. App. No. 62/712/172, entitled “System and Method for Massive MIMOCommunication” and filed Jul. 30, 2018, each of which is herebyincorporated by reference in its entirety for all purposes. In addition,this application hereby incorporates by reference, for all purposes,each of the following publications in their entirety for all purposes:U.S. Pat. App. Pub. Nos. US20140133456A1, US20150094114A1,US20150098385A1, US20150098387A1, US20160044531A1, US20170013513A1,US20170019375A1, US20170026845A1, US20170048710A1, US20170055186A1,US20170064621A1, US20170070436A1, US20170077979A1, US20170111482A1,US20170127409A1, US20170171828A1, US20170181119A1, US20170202006A1,US20170208560A1, US20170238278A1, US20170257133A1, US20170272330A1,US20170273134A1, US20170288813A1, US20170295510A1, US20170303163A1,US20170347307A1, US20180123950A1, US20180152865A1, and US20180299835A1;and U.S. Pat. Nos. 8,867,418, 8,879,416, 9,107,092, 9,113,352,9,232,547, and 9,455,959.

BACKGROUND

Massive MIMO radio transmitters are known to one of ordinary skill inthe art. In radio, multiple-input and multiple-output, or MIMO is amethod for multiplying the capacity of a radio link using multipletransmission and receiving antennas to exploit multipath propagation. Atone time, in wireless the term “MIMO” referred to the use of multipleantennas at the transmitter and the receiver. In modern usage, “MIMO”specifically refers to a practical technique for sending and receivingmore than one data signal simultaneously over the same radio channel byexploiting multipath propagation. MIMO is synergistically compatiblewith smart antenna techniques developed to enhance the performance of asingle data signal, such as beamforming and diversity. “Massive MIMO” isthe extension of the MIMO concept to use large antenna arrays tosimultaneously serve many autonomous terminals using multiple antennas,but using the smart antenna techniques of beamforming, etc. to providespatial multiplexing of many terminals in the same time-frequencyresource with high energy efficiency. A typical massive MIMO antenna isa 64T64R (T=transmit, R=receive) antenna array of substantial physicalsize.

In a rich scattering environment, the full advantages of the massiveMIMO system can be exploited using simple beamforming strategies such asmaximum ratio transmission (MRT), maximum ratio-combining (MRC) or zeroforcing (ZF). To achieve these benefits of massive MIMO, accuratechannel state information (CSI) must be available perfectly, and theM-MIMO radio antennas must be in perfect synch.

SUMMARY OF THE INVENTION

The invention relates generally to Multiple Input Multiple Output (MIMO)arrays, and in particular, microcomponent massive MIMO arrays using oneor more polar Power Amplifiers (PAs).

In an example embodiment, a microcomponent massive MIMO array isdisclosed comprising: a general purpose processor; an integrated poweramplifier and transmitter device including a Software Defined Radio(SDR) and a plurality of polar Power Amplifiers (PAs). The integratedpower amplifier and transmitter device is in communication with thegeneral purpose processor. An antenna array is in communication with theintegrated power amplifier and transmitter device. The presentlydisclosed microcomponent massive MIMO array uses a highly focused lowpower beam to transmit a high bandwidth data signal.

A microcomponent massive MIMO array comprising: a general purposeprocessor; an integrated power amplifier and transmitter deviceincluding a software defined radio (SDR) and a plurality of polar poweramplifiers (PAs) disposed on a single integrated circuit, wherein theintegrated power amplifier and transmitter device may be incommunication with the general purpose processor; and an antenna arrayin communication with the integrated power amplifier and transmitterdevice.

The microcomponent massive MIMO array may further comprise a basebandprocessor in communication with the general purpose processor and theintegrated power amplifier and transmitter device. The microcomponentmassive MIMO array may further comprise a digital pre-distortion (DPD)circuit integrated with the SDR. The digital pre-distortion (DPD) maycomprise a Field Programmable Gate Array (FPGA). An accelerator may beused in place of the FPGA. The microcomponent massive MIMO array mayfurther comprise a filter integrated with each polar PA. Themicrocomponent massive MIMO array may further comprise a duplexer forperforming Frequency Division Duplexing (FDD) disposed between an outputof the an integrated power amplifier and transmitter device and an inputto the antenna array. Each polar PA may comprise a one-quarter watt PA.A PA further may include a low noise amplifier (LNA), and/or a crestfactor reduction (CFR) circuit. An accelerator may be used in place ofthe SDR. The array may use a radio technology selected from the groupcomprising 2G, 3G, 4G and 5G. The array may be situated in a basestation. The array may be situated in an omnidirectional antenna array.The array may be situated in a mobile device.

Other aspects and advantages of the invention will become apparent fromthe following drawings, detailed description, and claims, all of whichillustrate the principles of the invention, by way of example only.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention and many attendantadvantages thereof will be readily obtained as the same becomes betterunderstood by reference to the following detailed description whenconsidered in connection with the accompanying drawings. In thedrawings, like reference characters generally refer to the same partsthroughout the different views. Further, the drawings are notnecessarily to scale, with emphasis instead generally being placed uponillustrating the principles of the invention.

FIG. 1A depicts a prior art diagram of power by scaling for a massiveMIMO system.

FIG. 1B depicts a prior art diagram of beamforming by synchronizationfor a massive MIMO system.

FIG. 1C depicts a prior art diagram of modularization for a massive MIMOsystem.

FIG. 2 depicts a prior art diagram of a massive MIMO system.

FIG. 3 depicts a prior art graph of power versus efficiency for a poweramplifier.

FIG. 4 depicts a diagram of a first microcomponent massive MIMO arrayarchitecture, in accordance with some embodiments.

FIG. 5 depicts a diagram of a phased array, in accordance with someembodiments.

FIG. 6 depicts a diagram of a second microcomponent massive MIMO arrayarchitecture, in accordance with some embodiments.

DETAILED DESCRIPTION

With the upcoming development of 5G radio technologies, it is desirableto have high bandwidth radio solutions that operate efficiently. Fromthis graph it can be seen that the power amplifier efficiency is muchlarger at 40 W power delivery than at 0.5 W or 1 W power delivery. Onetechnique being explored to enable higher bandwidth is called MassiveMIMO. According to this approach, multiple small independent antennaarrays are ganged together to output a MIMO signal. MIMO offers theadvantage that a beam can be pointed in a particular direction (i.e.,beamforming), which further enables the use of a highly-focused lowpower beam to effectively transmit a high bandwidth data signal.However, one obstacle to developing Massive MIMO technologies has beenpower efficiency of the radio transmit chain.

The radio transmit chain includes many components, including a basebandprocessor, an RF transmitter, a power amplifier, a filter (which may berequired to be customized to a particular set of frequencies), and anantenna, along with any necessary cabling. The baseband processorgenerates a digital signal, which is turned into radio pulses by the RFtransmitter (referred to herein as the “radio,” in some cases). Thepower amplifier (or PA) is used to amplify the radio pulses prior tooutput to the antenna. These power amplifiers are among the most powerhungry components in the RF chain, and in many cases are most efficientwhen saturated (configured to amplify at or near their maximum ratedoutput). It follows that when scaled down to lower power applications,power amplifiers become substantially less efficient. For example, fortransmissions at 1 W, a power amplifier rated at 4 W is not uncommon tobe required to avoid distorting the signal.

Certain techniques are known to improve the performance and powerefficiency of power amplifiers. For example, a technique is known calleddigital pre-distortion (DPD). DPD pre-distorts the input to the poweramplifier such that the output of the power amplifier is more linear,thereby increasing the power-efficient “sweet spot” of the poweramplifier. DPD provides a cost-effective linearization technique. DPDfeatures an excellent linearization capability, the ability to preserveoverall efficiency, and takes full advantage of advances in digitalsignal processors and AID converters. DPD adds an expanding nonlinearityin the baseband that complements the compressing characteristic of thePA. Ideally, the cascade of the pre-distorter and the power amplifierbecomes linear and the original input is amplified by a constant gain.With the pre-distorter, the power amplifier can be utilized up to itssaturation point while still maintaining good linearity, therebysignificantly increasing its efficiency.

However, DPD is expensive in multiple senses of the word. DPD requiresdigital circuits to provide this functionality, and these digitalcircuits require power to provide their functionality. For this reason,DPD is not commonly used for power amplifiers that output under 1 W oftransmit power.

This lack of efficiency has not been solved previously, as the majorityof commercial implementations require power output of 40 W to 80 W orabove. However, Massive MIMO has different characteristics, andspecifically requires DPD in order to provide beamforming. Where 2 40 WPAs could previously be used to output 80 W, or 4×20 W PAs to output 80W, the use of 64 or more transmitters to output 80 W requires high powerefficiency at 1.25 W. A new approach is required to handle this problem.

A massive MIMO requires high efficiency PAs. Generally, PAs are notefficient below 20-30 Watts (W), as 0.5-3 W are traditionally notconsidered useful. For delivering 80 W output with 64× MIMO, each RFchain needs a PA at 80÷64=1¼W. Another problem is that DPD (digitalpre-distortion) is needed for efficiency and it is required for MassiveMIMO. DPD must account for analog beamforming, which takes place afterthe baseband and after the DPD, which typically requires a tightcoupling between the DPD and the beamforming portion of the RF chain.But since DPD electronics are power-hungry, the secondary issue becomeshow to provide DPD for each channel without low efficiency. It simply isnot power-efficient to include DPD for each channel in the conventionalmanner when creating RF chains with a target output power of less than20-30 W.

Disclosed herein is an innovative integrated power amplifier and on-chiptransmitter. The inventors have made the key insight that a polar poweramplifier can be used in a high-efficiency RF chain without requiringDPD. This novel transmitter incorporates the polar PA, meaning that itprovides precise control of phase as well as amplitude of the outputsignal. Being able to control phase enables an array of such polartransmitters to form a phased array, which enables beamforming to beperformed without the power overhead of requiring DPD. This integratedPA and polar transmitter is thus the ideal building block for amicrocomponent massive MIMO array.

Control of phase by a polar transmitter array also enables complexmodulations and higher frequency transmissions, which is ideal for 5Gand other new RF technologies; as well, such a transmitter array is ableto emit higher-frequency, lower-wavelength waveforms, which is ideal forthe mmWave technologies proposed for 5G.

Traditional systems for MIMO arrays a general purpose processor, abaseband processor, a DPD element, a 40 W radio, a PA, a filter, andoptionally a duplexer for Frequency division duplexing (FDD). The poweramplifier in this scenario is most efficient at the 40 W power usage,and much less efficient in the 0.5 W to 1 W power usage.

Referring to FIGS. 1A-1C, the general idea of massive MIMO is shown. Asshown in FIG. 1A, a diagram 100 showing power by scaling is presented.Instead of using a single large antenna 101, multiple smaller antennas102 are used. As shown in FIG. 1B, a diagram 110 showing beamforming ispresented. An array of radio antennas 112 is synchronized bysynchronizer 111 to form multiple beams 113, 114, 115, which enablebeamforming to create beams directed to mobile devices 116, 117, 118. InFIG. 1C, a diagram showing modularization 120 is presented. Modules 121are created to facilitate synchronization without synchronizer 122.

FIG. 2 shows a prior art system 200 for providing a massive MIMO RFchain. The system 200 includes a general purpose processor 210 incommunication with a baseband processor 220. The baseband processor 220is used to perform baseband signal processing. DPD 230 is coupled to theoutput of the baseband processor 220, such that DPD is used to provideincreased linearity and thus power efficiency for the radio.

The output of the DPD 230 is provided to a radio 240. In this examplethe radio is shown as a 40 Watt (W) radio, though it should beunderstood that different power radios could also be used. The output ofradio 240 is fed to a single power amplifier 250. The 40 W radio isconfigured in combination with the DPD 230 and power amplifier 250 suchthat the combination is considered relatively power-efficient. Theoutput of the power amplifier is provided to filter 260. The filter isused to provide a particular set of frequencies.

An optional duplexer 270 for use when generating signals in FrequencyDivision Duplex (FDD) is shown connected to the output of the Filter260. The FDD utilizes a technique where separate frequency bands areused at the transmitter and receiver side. Because the FDD techniqueuses different frequency bands for send and receive operations, thesending and receiving data signals don't interfere with each other. Thisoften makes FDD a better choice than Time Division Duplex (TDD) forsymmetric traffic such as voice applications in broadband wirelessnetworks. While FDD is described herein, the techniques described applyalso to TDD systems.

The prior art system 200 shows a system that is considered state of theart for power efficiency. However, this system configuration (called theRF chain) is not power-efficient for lower-power radios.

FIG. 3 is a graph 300 having power values along a horizontal axis, andefficiency values along a vertical axis. The typical 40 W radio as shownin FIG. 2 has a highest efficiency at the 40 W power level, andsignificantly less efficiency at the 0.5 W and 1 W power levels as shownby line 310.

FIG. 4 shows a first embodiment of a system for providing amicrocomponent massive MIMO array 400. The system 400 includes a generalpurpose processor 402 in communication with a baseband processor 404.The baseband processor 404 is used to perform baseband signalprocessing.

Also shown is an integrated power amplifier and transmitter device 406in communication with the baseband processor. The integrated poweramplifier and transmitter device 406 includes a Software Defined Radio(SDR) 408 and one or more polar Power Amplifiers (PAs) 410. The SDR mayinclude a Field Programmable Gate Array (FPGA) for providing digitalpre-distortion (DPD). The polar PAs enable precise control of phase forhigh efficiency at the on-chip PA, as well as enabling beamforming evenwhen ganged together in a MIMO array.

A Low Noise Amplifier (LNA) (not shown) may also be included as part ofthe integrated power amplifier and transmitter device 406. An LNA is atype of electronic amplifier that amplifies a very low-power signalwithout significantly degrading its signal-to-noise ratio. A CrestFactor Reduction (CFR) device (not shown) may also be included as partof the integrated power amplifier and transmitter device 406. A CFRdevice is used to reduce the Peak to Average Power Ratio (PAPR) of thetransmitted signals so that the power amplifier can operate moreefficiently.

An optional Frequency Division Duplexer (FDD) 412 is shown connected tothe output of the integrated power amplifier and transmitter device 406,for use with FDD signal generation. Also shown is the direct output tothe Antenna array 414.

In some example embodiments, accelerators can be used in place of SDR,FPGAs and can provide DPD if needed. Filtering can be provided by theinclusion of a filter on each PA chip, or as one or more externalfilters (connected between the output and the RF emitter in the antennaarray). Accelerators as used herein could mean any 2G, 3G, 4G, 5G PHY,hard-coded logic module; or, they could mean any logic module providingFourier transforms (FFTs) and other math functionality.

A single system-on-chip could provide baseband on one chip and theentire RF chain on another chip, including: a software-defined radio(SDR); 2 W PA; low-noise amplifier (LNA); filter; DPD and crest factorreduction (CFR) circuitry.

Alternately, the baseband chip could be omitted and this functionalitycould be performed by a general-purpose chip. Alternately, anywhere aradio chip is mentioned, a software-defined radio (SDR) could be used.Alternately, anywhere an FPGA, which is commonly used to implement anSDR, is mentioned, the FPGA could be replaced by a general purpose chipwith a special-purpose accelerator logic circuit built in.

Adding FPGA functionality to the digital radio chip is less costly thanrequiring an FPGA, as it is relatively cheap to add space to an existingdie. Additional DPD, CFR functionality could be added to the radio chipas well. Accelerators here could mean any 2G, 3G, 4G, 5G PHY, hard-codedlogic module; or, they could mean any logic module providing FFT andother math functionality.

In a beamforming array the transmit will be slightly different in eachelement, so the interference cancellation should be aware of how thattransmit is shifted. In some embodiments, a power amplifier with sharpcontrol over amplification can be used, to generate a carrier withlimited noise.

Referring now to FIG. 5, a phased array 500 is shown. The phased arrayincludes an array of microcomponent radio elements 506, powered by afeed signal 502. The feed signal passes through the plurality ofmicrocomponent radio elements (506 a-506 n), which may each be in theform shown in FIG. 4 as radio chip 400, and controlled by a computer504. The wavefronts of the radio waves emitted by each element 508 a-508n are shown. The individual wavefronts are spherical, but they combine(superpose) in front of the antenna to create a plane wave, a beam ofradio waves traveling in a specific direction by having each antennaemits its wavefront later than the one below it, with the resultingplane wave to be directed at an angle θ to the antenna's axis. Due tothe use of polar power amplifiers, it is possible to combine multipleradio chips 506 a-506 n such that the output of these radio chips doesnot interfere and instead is able to be used to perform beamforming byadditively combining outputs of subsets of radio chips 506 a-506 n withhigh efficiency for power outputs less than 40 W.

Referring now to FIG. 6, a system 600 for providing a microcomponentmassive MIMO array is shown, in accordance with further embodiments. Thesystem 600 includes a general purpose processor 602 in communicationwith an integrated power amplifier and transmitter device 604. Theintegrated power amplifier and transmitter device 604 includes aSoftware Defined Radio (SDR) 108 with accelerators and a plurality ofpolar Power Amplifiers (PAs) 610 a-610 n. The polar PAs enable precisecontrol of phase for high efficiency at the on-chip PA, as well asenabling beamforming even when ganged together in a MIMO array. Alsoshown is a shared bus 606, used for communication among the SDR and thePAs. An optional duplexer for Frequency Division Duplex (FDD) 612 isshown connected to the output of the integrated power amplifier andtransmitter device 604. Also shown is the direct output to the antennaarray 614.

Accelerators can be used in place of or in combination with SDRs, FPGAsand can provide DPD if needed. Multiple accelerators are shownschematically as part of SDR 608, coupled between the SDR and the sharedbus 606. Any number of on-chip polar power amplifiers can be integratedonto the same system-on-chip, as well as any combination ofaccelerators. Multiple SDR units can provide additional processingpower. Since the SDR and polar PA units are all implemented in silicon,the chip can be scaled up or down to provide processing and radio outputpower for different processing needs and/or different power needs byadding/subtracting silicon logic units. The logic units may be FPGAs.

RF filtering can be provided on each PA chip, or as one or more externalfilters, connected between the output and the RF emitter in the antennaarray, providing flexibility for a single chip to be manufactured foruse across a wide variety of frequencies in conjunction with appropriatefilters.

Further details concerning the RF chain described herein are found inU.S. Provisional Pat. App. No. 62/712/172, entitled “System and Methodfor Massive MIMO Communication” and filed Jul. 30, 2018, herebyincorporated by reference.

The inventors have contemplated various additional variants of thepresent disclosure. A single system-on-chip could provide any of thefollowing combinations of circuitry on the same chip: integratedbaseband on the same chip; the entire RF chain on another chip, such RFchain including: a software-defined radio (SDR); 2 W PA; low-noiseamplifier (LNA); filter; DPD and crest factor reduction (CFR) circuitry.Alternately, the baseband chip could be omitted and this functionalitycould be performed by a general-purpose chip.

Alternately, anywhere a radio chip is mentioned, a software-definedradio (SDR) could be used. Alternately, anywhere an FPGA, which iscommonly used to implement an SDR, is mentioned, the FPGA could bereplaced by a general purpose chip with a special-purpose acceleratorlogic circuit built in. Adding FPGA functionality to the digital radiochip is less costly than requiring an FPGA, as it is relatively cheap toadd space to an existing die. Additional DPD, CFR functionality could beadded to a chip as well. Demodulation, decoding, and analysis/controlcould be performed by circuitry either on the same chip as the RF chainor baseband chip, or on a general purpose chip, or on an FPGA, or viaaccelerators.

Some embodiments of an apparatus may include: a plurality of transceivermodules configured in an antenna array; a synchronization transmissioncircuit configured to transmit a synchronization signal to the pluralityof transceiver modules; a receive carrier generation circuit configuredto generate a receive carrier reference signal; and a synchronizationprocessing circuit configured to process the synchronization signal andto align a phase of the receive carrier reference signal.

Some embodiments of an apparatus may include: a plurality of transceivermodules arranged in an array and configured to receive a digitalbaseband signal; a plurality of digital modulators and power amplifierseach configured to generate a transmit modulated signal from the digitalbaseband signal; and a combiner configured to combine the transmitmodulated signals.

Some embodiments of an apparatus may include: a plurality of antennaelements on a panel array; a plurality of transceiver modules arrangedon the panel array to be adjacent to one of the plurality of antennaelements and configured to receive a desired signal, wherein eachtransceiver module may include a plurality of digital demodulators, andincludes a baseband signal combiner; a demodulation circuit configuredto generate a demodulated baseband signal from each of the transceivermodules; and a combiner configured to combine the digital basebandsignals at the panel array using the baseband signal combiners.

In a further embodiment, an omnidirectional antenna is contemplated bythe inventors. Antenna elements formed according to the presentdisclosure are situated all around a single polar axis, enablingbeamforming to different users off of a single telephone antenna. Asingle round antenna with a plurality of elements is considered. Theround antenna may be shaped and may provide power for a base station ontop of a telephone pole. The round antenna may alternately be an antennafor a single handset. By use of a combination of ganged polar PAs asdescribed herein, beamforming is enabled even in a small antennapackage.

The foregoing discussion discloses and describes merely exemplaryembodiments of the present invention. As will be understood by thoseskilled in the art, the present invention may be embodied in otherspecific forms without departing from the spirit or essentialcharacteristics thereof. Various components in the devices describedherein may be added, removed, or substituted with those having the sameor similar functionality. Various steps as described in the figures andspecification may be added or removed from the processes describedherein, and the steps described may be performed in an alternativeorder, consistent with the spirit of the invention. Accordingly, thedisclosure of the present invention is intended to be illustrative, butnot limiting of the scope of the invention, as well as other claims. Thedisclosure, including any readily discernible variants of the teachingsherein, defines, in part, the scope of the foregoing claim terminology.

It is understood that any specific order or hierarchy of steps in theprocesses disclosed is an illustration of example approaches. Based upondesign preferences, it is understood that the specific order orhierarchy of steps in the processes may be rearranged, or that allillustrated steps be performed. Some of the steps may be performedsimultaneously. For example, in certain circumstances, multitasking andparallel processing may be advantageous. Moreover, the separation ofvarious system components illustrated above should not be understood asrequiring such separation, and it should be understood that thedescribed program components and system can generally be integratedtogether in a single software product or packaged into multiple softwareproducts.

The benefits, advantages, solutions to problems, and any element(s) thatmay cause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeatures or elements of any or all the claims. The invention is definedsolely by the appended claims including any amendments made during thependency of this application and all equivalents of those claims asissued.

These functions described above can be implemented in digital electroniccircuitry, in computer software, hardware, or firmware. The techniquescan be implemented using one or more computer program products.Programmable processors and computers can be included in or packaged asmobile devices. The process and logic flows can be performed by one ormore programmable processors and by one or more programmable logiccircuitry. General and special purpose computing devices and storagedevices can be interconnected through communication networks.

Some implementations include electronic components, for examplemicroprocessors, storage and memory that store computer programinstructions in a machine-readable or computer-readable medium(alternatively referred to as computer-readable storage media,machine-readable media, or machine-readable storage media). Someexamples of such computer-readable media include RAM, ROM, read-onlycompact discs (CD-ROM), readable compact discs (CD-R), rewritablecompact discs (CD-RW), read-only digital versatile discs (e.g., DVD-ROM,dual-layer DVD-ROM), a variety of recordable/rewritable DVDs (e.g.DVD-RAM, DVD-RW, DVD+RW, etc.), flash memory (e.g., SD cards, mini-SDcards, micro-SD cards, etc.), magnetic or solid-state hard drives,read-only and recordable Blu-Ray® discs, ultra-density optical discs,any other optical or magnetic media, and floppy disks. Thecomputer-readable media can store a computer program that is executed byat least one processing unit and includes sets of instructions forperforming various operations. Examples of computer programs or computercode include machine code, for example is produced by a compiler, andfiles including higher-level code that are executed by a computer, anelectronic component, or a microprocessor using an interpreter.

It will be appreciated that some embodiments may comprise one or moregeneric or specialized processors (or “processing devices”) such asmicroprocessors, digital signal processors, customized processors andfield programmable gate arrays (FPGAs) and unique stored programinstructions (including both software and firmware) that control the oneor more processors to implement, in conjunction with certainnon-processor circuits, some, most, or all of the functions of themethod and/or apparatus described herein. Alternatively, some or allfunctions could be implemented by a state machine that has no storedprogram instructions, or in one or more application specific integratedcircuits (ASICs), in which each function or some combinations of certainof the functions are implemented as custom logic. Of course, acombination of the two approaches could be used.

Accordingly, some embodiments of the present disclosure, or portionsthereof, may combine one or more processing devices with one or moresoftware components (e.g., program code, firmware, resident software,micro-code, etc.) stored in a tangible computer-readable memory device,which in combination form a specifically configured apparatus thatperforms the functions as described herein. These combinations that formspecially programmed devices may be generally referred to herein as“modules.” The software component portions of the modules may be writtenin any computer language and may be a portion of a monolithic code base,or may be developed in more discrete code portions such as is typical inobject-oriented computer languages. In addition, the modules may bedistributed across a plurality of computer platforms, servers,terminals, and the like. A given module may even be implemented suchthat separate processor devices and/or computing hardware platformsperform the described functions.

Moreover, an embodiment can be implemented as a computer-readablestorage medium having computer readable code stored thereon forprogramming a computer (e.g., comprising a processor) to perform amethod as described and claimed herein. Examples of suchcomputer-readable storage media include, but are not limited to, a harddisk, a CD-ROM, an optical storage device, a magnetic storage device, aROM (Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM(Erasable Programmable Read Only Memory), an EEPROM (ElectricallyErasable Programmable Read Only Memory) and a Flash memory. Further, itis expected that one of ordinary skill, notwithstanding possiblysignificant effort and many design choices motivated by, for example,available time, current technology, and economic considerations, whenguided by the concepts and principles disclosed herein will be readilycapable of generating such software instructions and programs and ICswith minimal experimentation.

Various modifications to these aspects will be readily apparent, and thegeneric principles defined herein may be applied to other aspects. Thus,the claims are not intended to be limited to the aspects shown herein,but is to be accorded the full scope consistent with the languageclaims, where reference to an element in singular is not intended tomean “one and only one” unless specifically so states, but rather “oneor more.” Unless expressly stated otherwise, the term “some” refers toone or more. Pronouns in the masculine (e.g., his) include the feminineand neuter gender (e.g., her and its) and vice versa. Headings andsubheadings, if any, are used for convenience only, and do not limit thesubject technology.

A phrase, for example, an “aspect” or “feature” does not imply that theaspect is essential to the subject technology or that the aspect appliesto all configurations of the subject technology. A disclosure relatingto an aspect may apply to all configurations, or one or moreconfigurations. A phrase, for example, an aspect may refer to one ormore aspects and vice versa. A phrase, for example, a “configuration”does not imply that such configuration is essential to the subjecttechnology or that such configuration applies to all configurations ofthe subject technology. A disclosure relating to a configuration mayapply to all configurations or one or more configurations. A phrase, forexample, a configuration may refer to one or more configurations andvice versa.

The foregoing discussion discloses and describes merely exemplaryembodiments of the present invention. In some embodiments, softwarethat, when executed, causes a device to perform the methods describedherein may be stored on a computer-readable medium such as a computermemory storage device, a hard disk, a flash drive, an optical disc, orthe like. As will be understood by those skilled in the art, the presentinvention may be embodied in other specific forms without departing fromthe spirit or essential characteristics thereof. Various components inthe devices described herein may be added, removed, or substituted withthose having the same or similar functionality. Various steps asdescribed in the figures and specification may be added or removed fromthe processes described herein, and the steps described may be performedin an alternative order, consistent with the spirit of the invention.Accordingly, the disclosure of the present invention is intended to beillustrative of, but not limiting of, the scope of the invention, whichis specified in the following claims.

What is claimed is:
 1. A microcomponent massive Multiple Input MultipleOutput (MIMO) array comprising: a general purpose processor; anintegrated power amplifier and transmitter device including a softwaredefined radio (SDR) and a plurality of power amplifiers (PAs), the SDRand the plurality of PAs disposed together on a single integratedcircuit, wherein the plurality of PAs provide precise control of thephase thereby enabling an array of PAs to form a phased array enablingbeam forming to be performed, wherein the integrated power amplifier andtransmitter device is in communication with the general purposeprocessor; and an antenna array in communication with the integratedpower amplifier and transmitter device, wherein the SDR comprises aField Programmable Gate Array (FPGA) functionality and wherein a digitalpre-distortion (DPD) circuit is also included as part of the FPGAfunctionality.
 2. The microcomponent massive MIMO array of claim 1,further comprising a baseband processor in communication with thegeneral purpose processor and the integrated power amplifier andtransmitter device.
 3. The microcomponent massive MIMO array of claim 1,further comprising a DPD circuit integrated with the SDR.
 4. Themicrocomponent massive MIMO array of claim 1, wherein an accelerator isused in place of the FPGA.
 5. The microcomponent massive MIMO array ofclaim 1, further comprising a filter integrated with each polar PA. 6.The microcomponent massive MIMO array of claim 1, further comprising aduplexer for performing Frequency Division Duplexing (FDD) disposedbetween an output of the integrated power amplifier and transmitterdevice and an input to the antenna array.
 7. The microcomponent massiveMIMO array of claim 1, wherein each polar PA comprises a one-quarterwatt (W) PA.
 8. The microcomponent massive MIMO array of claim 1,wherein the PA further includes a low noise amplifier (LNA).
 9. Themicrocomponent massive MIMO array of claim 1, wherein the PA furtherincludes a crest factor reduction (CFR) circuit.
 10. The microcomponentmassive MIMO array of claim 1, wherein an accelerator is used in placeof the SDR.
 11. The microcomponent massive MIMO array of claim 1,wherein the array uses a radio technology selected from the groupcomprising 2G, 3G, 4G and 5G.
 12. The microcomponent massive MIMO arrayof claim 1, wherein the array is situated in a base station.
 13. Themicrocomponent massive MIMO array of claim 1, wherein the array is anomnidirectional antenna array and is situated in a mobile device. 14.The microcomponent massive MIMO array of claim 1, wherein the pluralityof power amplifiers comprise a plurality of polar power amplifiers. 15.A microcomponent massive Multiple Input Multiple Output (MIMO) arraycomprising: a general purpose processor; an integrated power amplifierand transmitter device including a software defined radio (SDR) and aplurality of power amplifiers (PAs), wherein the plurality of PAsprovide precise control of the phase thereby enabling an array of PAs toform a phased array enabling beamforming to be performed, wherein theintegrated power amplifier and transmitter device is in communicationwith the general purpose processor; and an antenna array incommunication with the integrated power amplifier and transmitterdevice, wherein the SDR comprises a Field Programmable Gate Array (FPGA)functionality and wherein a digital pre-distortion (DPD) circuit is alsoincluded as part of the FPGA functionality.